1. Field of the Invention
The present invention generally relates to error processing methods and information processing apparatuses, and more particularly to an error processing method for processing a bus error that is generated in an instruction bus or a data bus, and an information processing apparatus provided with a CPU or the like having a Harvard architecture.
2. Description of the Related Art
For use in vehicles and the like, there are demands to provide a parity check or ECC check function for a memory part in a CPU of a microprocessor. In the conventional CPU, if an error is generated during a bus access, the correct instruction code cannot be supplied to the CPU, and the CPU has to be halted. One method of avoiding such a halting of the CPU is to input an external interrupt to the CPU when the error is generated during the bus access, but according to this method, there is a possibility of executing the instruction code for which the bus error is generated before a jump is made to the interrupt routine. In addition, since the CPU does not always execute the instruction code that makes the bus access, as in the case of the jump instruction, there is a possibility of generating a meaningless interrupt.
Furthermore, in the case where the CPU has the Harvard architecture in which the instruction bus and the data bus are separate, there is a possibility that, after a bus error is generated on the instruction bus for a certain instruction, a data bus error will be generated for an instruction that is executed before the certain instruction. For this reason, it is necessary to process the data bus error with a priority over the instruction bus error. For example, the FR series Reduced Instruction Set Computer (RISC) microcomputer manufactured by Fujitsu Limited of Japan is one example of the microprocessor provided with the CPU having the Harvard architecture. In such a CPU, if an undefined instruction is generated, an exception handler within an instruction sequencer of an instruction decoder part is started, so as to generate instructions for fetching a start address of an undefined interrupt routine and instructions for saving contents of a Processor Status (PS) register that indicates the CPU status and a Program Counter (PC) register by an Exception Interrupt Trap (EIT) process, and to jump to the interrupt routine.
FIG. 1 is a system block diagram showing a structure of an important part of a conventional CPU. The conventional CPU shown in FIG. 1 generally includes a fetch part (F-part) 101, a decode part (D-part) 102, an execute part (E-part) 103, a memory access part (M-part) 104, and a general-purpose register part 105.
The F-part 101 carries out an instruction fetch to acquire the instruction code using an internal instruction bus Ibus. The fetched instruction code is set in an intermediate register Tf, and the address in this state is set in an intermediate register Tia_f. The F-part 101 includes an Ibus access controller 111.
The D-part 102 interprets the fetched instruction code, and prepares the data necessary for the operation (or computation) and the operation mode (addition, subtraction, etc.) to be executed by the E-part 103. More particularly, the operation mode of an operation unit (ALU) 132 within the E-part 103 is decoded from the fetched instruction code, and register values to be used for the operation are set in intermediate registers Ta and Tb. A value to be written is set in an intermediate register Tdd when writing via an internal data bus Dbus. When an internal error caused by an external interrupt, an undefined instruction or the like is generated, an exception handler 122 within an instruction sequencer 121 jumps to an interrupt routine, and thus, the D-part 102 automatically supplies instructions for reading an interrupt vector table and saving contents of the PS register and the PC register of the general-purpose register part 105. A decoder 123 and a multiplexer 124 are provided within the instruction sequencer 121. The D-part 102 includes an intermediate register Tdec for latching the operation mode that is decoded by the instruction sequencer 121, a matrix (or selector) 125, and a multiplexer 126.
FIG. 2 is a flow chart for explaining an operation of the instruction sequencer 121 within the D-part 102 of the conventional CPU. After newly fetching an instruction code, the instruction code is input to the D-part 102 (step S1), and the instruction code is decoded (step S2). If the instruction code is normal as a result of the decoding, the operation mode of the instruction and the contents of the general-purpose register part 105 necessary for the operation are set in the intermediate registers Tdec, Ta, Tb and Tdd, and supplied to the E-part 103 (step S3). Thereafter, in the next cycle, the next instruction is input and the decoding is started.
If the decoded result is an undefined instruction or an external interrupt, the vector address is acquired from the vector table so as to jump to the routine of the exception interrupt, and the operation mode for computing the jump address and the contents of the general-purpose register part 105 necessary for the operation are supplied to the E-part 103 (step S4). The technique which uses the vector table is often used as a method of jumping to the exception process, because the data of each address within the vector table points to the start address of the corresponding exception process, and the data of each address is also referred to as the vector address. In the next cycle, the operation mode for saving the content of the PS register and the contents of the general-purpose register part 105 necessary for the operation are supplied to the E-part 103 (step S5). Thereafter, the operation mode for saving the content of the PC register and the contents of the general-purpose register part 105 necessary for the operation are supplied to the E-part 103 (step S6). The steps S4 through S6 form the EIT process. Thereafter, a check is made to determine the existence of other interrupts or errors (step S7), and the next instruction is decoded if no other interrupt or error exists (No in step S7). On the other hand, the vector address acquisition by the EIT process is repeated if other interrupt or error exists (YES in step S7).
The E-part 103 receives the operation mode signal and the operation data from the D-part 102, and carries out the operation. More particularly, the E-part 103 carries out the operation of the instruction, and sets a result obtained by the operation unit 132 in an intermediate register Te. If a register hazard is generated due to the combination of instructions, the E-part 103 uses a register bypass route 131 to directly set the intermediate registers Ta or Tb and Tdd for making input to the E-part 103 from the output of the operation unit 132. The E-part 103 includes an intermediate register Ted that is set with the output of the intermediate register Tdd within the D-part 102.
The M-part 104 receives the data from the E-part 103, and makes a write or read with respect to the memory part using the internal data bus Dbus. More particularly, the M-part 104 makes a write or read with respect to the memory part, the general-purpose register part 105 (PC, R0 to R15) or the like for the operation result of the instruction. The M-part 104 includes an intermediate register Tia_m and a Dbus access controller 141.
The general-purpose register part 105 forms the internal registers of the CPU, and includes the PC register, the PS register, the operation registers R0 to R15, and a multiplexer 151.
In FIG. 1, ID denotes an instruction code, IA denotes the address of the instruction code, and iaccess, irdy, IRDY and ISZE respectively denote the access request of the instruction code, the ready output of the instruction code, the ready input of the instruction code, and the size of the instruction code. In addition, DA, DDout and DDin respectively denote the address of the data, the output data, and the input data. Furthermore, daccess, drdy, DRDY and DSIZE respectively denote the access request of the data, the ready output of the data, the ready input of the data, and the size of the data.
The address of the instruction is stored in the intermediate registers Tia_f→Ria_dec→Tia_e→Tia_m of the parts 101 through 104. If the operation result is set in the operation register Ri (i=0 to 15) for a certain instruction and the operation register Ri is to be used for the next instruction, the operation result set in the operation register Ri will not reach the D-part 102 in time. For this reason, a route that enables the output of the operation unit 132 to be set in the intermediate register Ta or Tb, that is, the register bypass route 131, is provided.
The processes of the instructions are carried out in the order in which the instructions are fetched by the CPU. Each instruction successively transferred to the F-part 101, the D-part 102, the E-part 103 and the M-part 104, every time one clock is input, and the CPU operates according to the instruction. If an instruction I1 is fetched by the F-part 101 and this instruction I1 is transferred to the D-part 102 in response to the next clock, the F-part 101 simultaneously fetches an instruction 12 in response to this next clock. Such an operation is repeated, and a pipeline processing of the instructions 11 through 15 is made, as shown in FIGS. 3 through 8. FIG. 3 is a timing chart for explaining the operation of the conventional CPU. FIG. 4 is a diagram for explaining a state (1) shown in FIG. 3, FIG. 5 is a diagram for explaining a state (2) shown in FIG. 3, FIG. 6 is a diagram for explaining a state (3) shown in FIG. 3, FIG. 7 is a diagram for explaining a state (4) shown in FIG. 3, and FIG. 8 is a diagram for explaining a state (5) shown in FIG. 3. In FIGS. 4 through 8, nop denotes a “no operation”.
The conventional CPU does not have a bus error input means. Hence, if an error such as a parity error is generated in the memory part, an instruction that is executable by the CPU cannot be prepared externally, and the CPU halts. In addition, if the CPU fetches the instruction, detects a parity error, and uses an external interrupt to indicate the parity error detection, there is a possibility of executing the instruction for which the bus error is generated. Moreover, even if the CPU fetches the instruction and detects the parity error, when the fetched instruction is not executed due to execution of a jump instruction or the like, a meaningless interrupt will be generated. Furthermore, if the bus error is generated on the instruction bus, the data bus error for the immediately preceding instruction is generated later, and it is necessary to take into consideration the priority order of the processes.
For example, a Japanese Laid-Open Patent Application No. 6-242977 proposes a 1-chip microprocessor that is constructed to detect the parity error of the address of data.
Therefore, according to the conventional CPU having the Harvard architecture, there was a problem in that it is difficult to appropriately process a bus error that is generated on an instruction bus or a data bus.